1. Field of the Invention
The present invention generally relates to an integrated circuit chip structure that has a chip level test access port (TAP) controller and more particularly to a chip that also includes a plurality of embedded TAPs connected to the chip level TAP. Because the embedded TAPs have instruction register (IR) lengths that differ from the chip level TAP IR, and the embedded TAP IR lengths may differ from each other, the chip level TAP includes a flexible length instruction register architecture designed to accommodate the different length instruction registers of the embedded TAPs while using a constant length chip level instruction register definition for all IR accesses through the chip level TAP.
2. Description of the Related Art
As explained in U.S. Pat. No. 6,334,198 (incorporated herein are reference), the electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A wide variety of techniques have been used in IC devices to ensure that, once they are manufactured, they operate fully in compliance with their intended design and implementation specifications. Many of the more complex IC designs include circuits that permit in-circuit testing via the IC access pins. The IEEE 1149.1 JTAG recommendation, for example, provides a test circuit architecture for use inside such ICs. This architecture includes a test access port (TAP) controller coupled to the IC pins for providing access to and for controlling various standard features designed into such ICs. Some of these features are internal scan, boundary scan, built-in test, and emulation.
The JTAG recommendation was developed with the understanding that such IC designs would be using only one TAP controller. Sometime after the TAPs, initial development, however, many IC's were designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. Typically, separate IC pins are used to select one of the TAP controllers for testing and/or debugging the IC. This is problematic, however, in IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins.
ASIC (application specific integrated circuit) devices, usually contain a single JTAG TAP controller for access and control of board level tests of I/O continuity. Access to user defined functions can also be supported using the chip level TAP controller and private instruction definitions. When integrating large intellectual property (IP) blocks into today's ASICs there is the possibility that such IP will have embedded JTAG access through a self contained TAP controller. Access methods for embedded TAP functions are not covered in the IEEE 1149.1 JTAG specification. Methods have evolved, independent of the IEEE 1149.1 specification, that enable access to embedded TAP controllers through the use of various implementations of compliance enable logic and private instruction definitions in the ASICs chip level TAP controller. These methods strive to maintain IEEE 1149.1 JTAG compliance; however, one limitation of these existing methods is the inability to shift out (or read) differing length embedded TAP instruction registers with a single chip level instruction register length definition as is required for IEEE 1149.1 compliance.
This invention described below allows IEEE 1149.1 compliant shifting out (reading) of embedded JTAG TAP controller instruction register (IR) contents, contained in IP blocks on ASIC chips, while using a constant length chip level instruction register definition for all IR accesses through the chip level TAP.